
`timescale 1ns / 1ns




module tb_RD_interface();



reg i_clk, i_rst;
wire RDflag, RD_finish;
reg rd_trig;
reg [7:0] RD_addr;




wire chip_oeRD;
wire [7:0] read_data;
reg [7:0] i_sja1000_data_rdRD;
wire [7:0] sja1000_data_wrRD;
wire sja1000_rd_nRD;
wire sja1000_aleRD;
wire sja1000_cs_nRD;
wire sja1000_dir_outRD;






RD_interface RD_interface_inst(
. i_clk(i_clk),
. i_rst(i_rst), 

. o_RDflag(RDflag), 

. rd_trig(rd_trig), 
. RD_addr(RD_addr),
 
. o_read_data(read_data), 
. o_RD_finish(RD_finish), 

. i_sja1000_data_rd(i_sja1000_data_rdRD), //读的数据
. o_chip_oe(chip_oeRD),//有读有写 
. o_sja1000_data_wr(sja1000_data_wrRD), //写的地址
. o_sja1000_rd_n(sja1000_rd_nRD), 
. o_sja1000_ale(sja1000_aleRD),
. o_sja1000_cs_n(sja1000_cs_nRD),
. o_sja1000_dir_1out(sja1000_dir_outRD));//有读有写




 initial begin
    i_clk = 1'b0;
	i_rst = 1'b1;
    #20
    i_rst = 1'b0;
    i_sja1000_data_rdRD <= 8'h00;
    
    /////////////
	

    #1
    rd_trig = 1'b1;
	RD_addr = 8'h1F;
    #2
    i_sja1000_data_rdRD <= 8'hA3;
	rd_trig = 1'b0;
	RD_addr = 8'h0;
	
	
    #50
    rd_trig = 1'b1;
	RD_addr = 8'h2E;
    #2
    i_sja1000_data_rdRD <= 8'hB2;
	rd_trig = 1'b0;
	RD_addr = 8'h0;
	
	
	#50
    rd_trig = 1'b1;
	RD_addr = 8'h3D;
    #2
    i_sja1000_data_rdRD <= 8'hC1;
	rd_trig = 1'b0;
	RD_addr = 8'h0;
	
	end 
	
always#1 i_clk = ~i_clk;

 
 
 //表示在对应寄存器之中的存储值
 
 
 
 
 
   
   
endmodule

